FIG. 1 shows a structure of a variable speed driver using a voltage type PWM (Pulse Width Modulation) inverter disclosed in a Japanese Patent Application No. Heisei-2-7983 filed on Jan. 17, 1990.
In FIG. 1, numeral 1 denotes a vector control section using data on a speed or torque instruction and speed detection and so forth, numeral 2 denotes an ACR (current) control section which carries out current control calculations in response to a current instruction derived from the vector control section, numeral 3 denotes a PWM pattern generator which calculates a three-phase PWM pattern according to a voltage amplitude of a voltage space vector and phase instruction derived from the ACR control section and issues a PWM instruction on the basis of the calculated PWM pattern, numeral 4 denotes a dead time compensator, numeral 5 denotes a gate signal circuit, numeral 6 denotes a drive circuit, numeral 7 denotes an inverter circuit, and numeral 8 denotes an induction motor.
Furthermore, in FIG. 1, numeral 9 denotes a voltage detector, numeral 10 denotes a current detector, numeral 11 denotes a speed detector, numeral 12 denotes a sample hold circuit which holds an instantaneous output current in synchronization with an intermediate sample hold signal of a 0 (zero) vector from the PWM pattern generator until an A/I) conversion is carried out, numeral 13 denotes an A/D converter, numeral 22 denotes an adder which derives a power supply speed .omega..sub.o from a rotor speed .omega..sub.r of the speed detector 11 and a slip angular velocity .omega..sub.s.
FIG. 5 shows a circuit block of the PWM pattern generator 3. In FIG. 5, numeral 31 denotes a PWM pattern calculation block which receives a voltage instruction .vertline. V.vertline. derived from the ACR control section 1, an output voltage phase .phi. restriced between 60.degree. from an output voltage phase instruction .theta.v, a DC power supply voltage Vdc, and PWM carrier wave period (PWM time) Tc, calculates the PWM pattern using a circle approximation method, and outputs voltage vector times T.lambda. and T.mu. whose phases are mutually different by 60.degree., and 0 vector time To.
Next, numeral 32 denotes a three-arm modulating time data preparation section which prepares time data such that 0 vector time To is divided into half To/2 to both sides of the voltage vector times T.lambda. and T.mu. during a half PWM time Tc/2 as shown in FIG. 6 and outputs time data of T.sub.1, T.sub.2, and T.sub.3.
In addition, numeral 33 denotes a time changeover switch which converts the time data of T.sub.1, T.sub.2, and T.sub.3 into each phase voltage time Tu, Tv, and Tw and numeral 24 denotes and ON/OFF switching circuit which performs the switching of Tu, Tv, and Tw and outputs each please voltage signal Vu, Vv, and Vw (PWM pattern).
It is noted that, in FIG. 5, numeral 35 denotes a mode selection circuit for every 60.degree. of the output voltage phase .theta.v from the ACR control section, numeral 36 denotes a reference phase output table which receives the output signal of the every-60.degree. mode circuit 35 and outputs a reference phase .phi..lambda. for every 60.degree., numeral 37 (namely, a symbol .+-..largecircle. in FIG. 5) denotes a subtractor which subtracts the reference phase .phi..lambda. for every 60.degree. from the output voltage phase .phi.v and outputs the output voltage phase .phi. restricted between 60.degree. to the PWM pattern calculation block 31, numeral 38 denotes a switch selection table which controls the time changeover switch 33 according to the output of the every-60.degree. mode selection circuit 35 for every 60.degree., and numeral 39 denotes a switching ON/OFF control circuit which controls the ON/OFF switching circuit according to the PWM time Tc and performs the sampling operation for the current.
Anyway, the above-described PWM pattern is calculated using the circle approximation method with 0 vector time To being divided into half To/2 to be inserted into both sides of the times T.lambda. and T.mu. to output the times data and with the current being coupled at an interval point of the PWM pattern (this is hereinafter referred to as a three-arm modulation method). This methos resulted in such a way that as the output voltage becomes higher, a width of 0 vector becomes narrower.
As the width of 0 vector becomes narrower, a defect (nullfied or defeciency of 0 vector (hereinafter, referred to simply as 0 vector defect) occurs due to a dead time compensation. At this time, a locus of a current vector is moved toward a direction at which a radius becomes larger.
FIGS. 7 (A) and 7 (B) show vectors before 0 vector defect and those after 0 vector defect. As shown in FIG. 7 (B), 0 vector interval of time at a point B is moved to a point D due to the dead time compensation. In a case where 0 vector is defected at the point of B and 0 vector appears earlier at the point of D, a locus of the current vector is as shown in FIG. 8.
In this case, the locus of the current vector is the same at points of .left brkt-top.5.right brkt-bot. and .left brkt-top.6.right brkt-bot. but the locus thereof becomes long in time at a point of .left brkt-top.3.right brkt-bot..
Therefore, the current vector is accordingly moved largely. Since the current vectors at points of .left brkt-top.5.right brkt-bot. and .left brkt-top.6.right brkt-bot. remains unmoved, the current vector is present at a position translated from the points of .left brkt-top.5.right brkt-bot. and .left brkt-top.6.right brkt-bot. by an interval elongated at the point off .left brkt-top.3.right brkt-bot. as compared with a locus of a current vector (not shown) in the case of FIG. 7 (A) in which 0 vector is not defected. The interval of time of the vector at a point of .left brkt-top.7.right brkt-bot. becomes shorter by the increase in the 0 vector. The 0 vector interval at a point of .left brkt-top.8.right brkt-bot. becomes longer by 0 vector interval which should be in the interval of .left brkt-top.3.right brkt-bot.. Consequently, an end of .left brkt-top.9.right brkt-bot. coincides with a point of the beginning of .left brkt-top.1.right brkt-bot..
In other words, if 0 vector defect occurs, a point of the final locus of the current vector becomes equal to a part wherein 0 vector is not present. However, the locus during that interval is translated toward a direction at which the current radius becomes large. Therefore, an integrated value of the current at that interval becomes larger than that of the current in which 0 vector defect is not present. Consequently, the current becomes different according to a position in which 0 vector is inserted even though the PWM pattern is generated with the same voltage component.
With the above-described problem in mind, it is an object of the present invention to provide an apparatus and method for carrying out a current control for a variable speed driver which improves the ACR control characteristic at a position placed in a proximity to a voltage saturation by exchanging the PWM pattern from the three-arm modulation method to the two-arm modulation method at a vicinity to the voltage saturation, the ACR control system being unchanged.